The present disclosure relates to the field of DRAM (dynamic random access memory) circuits with integrated processors, and methods of communication with such memories.
Modern computers generally comprise a processing circuit, often implemented as a system on chip (SoC), coupled to one or more dynamic random access memory (DRAM) circuits. Such memories, which generally require a periodic refresh operation, are dense and relatively fast to access, and are thus used as the main RAM data storage in most computers. However, in view of the ever increasing amounts of data to be transferred between the SoC and DRAM circuits, such data transfers tend to slow the operation of the computer and lead to a relatively high energy consumption.
A solution that has been proposed is to provide DRAM circuits having one or more processors integrated therein, in addition to the processors in the SoC. Such a solution reduces the level of data transfer between the DRAM circuit and the SoC by allowing certain processing tasks to be delegated to the DRAM processors, so that these processing tasks can be performed while avoiding data transfer between the DRAM circuit and the SoC.
However, a challenge in providing a DRAM circuit with integrated processors is that the interface with the SoC is time consuming and costly to implement.
International patent application published as WO2010/141221 describes a system and method for arbitrating access to a memory array associated with an internal processor. The arbitration involves interfacing an external processor, comprising a memory controller, with the internal processor through a control interface formed of electrical connections for communicating request and grant signals.
A problem in systems such as the one described in the publication WO2010/141221 is that the external processor incorporating the memory controller must be modified in order to permit the arbitration control signals to be communicated to and from the internal processor, leading to a solution that is costly and complex.